Method of providing an operating voltage in a memory device and a memory controller for the memory device

ABSTRACT

A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of U.S. application Ser. No.13/289,282 filed on Nov. 4, 2011, which claims priority under 35 U.S.C.119 to Korean Patent Application No. 10-2010-0112110 filed on Nov. 11,2010, the disclosures of which are incorporated by reference herein intheir entireties.

BACKGROUND OF THE INVENTIVE CONCEPT

1. Technical Field

The present inventive concept relates to a method of providing anoperating voltage in a memory device and a memory controller, and moreparticularly to a method of controlling an operating voltage applied toan unselected word line in a memory device.

2. Discussion of the Related Art

After an erase/program operation is performed on a selected memory cellin a memory device, a trap charge occurs at an edge of a tunnelisolation layer in the memory transistor of the selected memory cell.The increase of the trap charge causes a decrease of memory cell currentand an increase of the threshold voltage for turning the memorytransistor of the selected memory cell ON. In other words, after theerase/program operation of the memory device, the threshold voltage ofmemory cells increases, expanding a threshold voltage distribution.

In a read operation, a read voltage V_(READ) is applied to a selectedword line connected to a memory cell from which data will be read and apass voltage V_(PASS) is applied to unselected word lines (i.e., wordlines other than the selected word line) to turn ON memory cellsconnected to the unselected word lines.

At this time, when the threshold voltage of a memory cell is lower thanthat of adjacent memory cells, an electric field applied to a tunnelisolation layer of the memory cell having the lower threshold voltage isreduced by the memory cells having the higher threshold voltage.

As a result, the threshold voltage distribution of the memory cellhaving the lower threshold voltage is more expanded.

SUMMARY

Some embodiments of the present inventive concept provide a method ofproviding an operating voltage in a memory device, thereby improving thecharacteristic of the threshold voltage distribution of memory cells,and a memory controller.

According to some embodiments of the present inventive concept, there isprovided a method of providing an operating voltage in a memory device.The method includes the steps of applying a read voltage to a selectedword line; applying a first pass voltage to at least one word line amongword lines adjacent to the selected word line; and applying a secondpass voltage to word lines other than the selected word line and the atleast one word line to which the first pass voltage is applied. Thelevel of the first pass voltage may be higher than the level of thesecond pass voltage.

The steps of applying the first pass voltage may include changing thelevel of the first pass voltage and applying the first pass voltage at adifferent level according to the level of the read voltage.

The changing and applying the first pass voltage may include setting thelevel difference between the first pass voltage and the read voltage toa predetermined value.

The read voltage may include a verify read voltage used in incrementalstep pulse programming (ISPP) and a read voltage used in a readoperation.

When the read voltage comprises a minus voltage, the changing andapplying the first pass voltage may include applying the first passvoltage at different levels according to whether the read voltage is theminus voltage or not.

According to other embodiments of the present inventive concept, thereis provided a memory device including a voltage generator configured toprovide an operating voltage necessary for an operation of the memorydevice to a memory array; and a chip controller configured to controlthe voltage generator to apply a read voltage to a selected word line inthe memory array, to apply a first pass voltage to at least one wordline among unselected word lines adjacent to the selected word line, andto apply a second pass voltage to unselected word lines (other than theat least one word line to which the first pass voltage is applied). Thelevel of the first pass voltage may be higher than the level of thesecond pass voltage.

The chip controller may control the voltage generator to change thelevel of the first pass voltage and apply the first pass voltage at adifferent level based on the level of the read voltage.

The chip controller may control the voltage generator to set the leveldifference between the first pass voltage and the read voltage to apredetermined value.

According to further embodiments of the present inventive concept, thereis provided a memory system including a memory device; and a memorycontroller configured to control the memory device to apply a readvoltage to a selected word line in the memory device, apply a first passvoltage to at least one word line among word lines adjacent to theselected word line, and apply a second pass voltage to word lines otherthan the selected word line and the at least one word line to which thefirst pass voltage is applied.

The memory device may include a memory array and a voltage generatorconfigured to provide an operating voltage necessary for an operation ofthe memory device to the memory array based on control of the memorycontroller.

The present inventive concept now will be described more fullyhereinafter with reference to the accompanying drawings, in whichembodiments of the inventive concept are shown. This inventive conceptmay, however, be embodied in many different forms and should not beconstrued as limited to the embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the inventive concept tothose skilled in the art. In the drawings, the size and relative sizesof layers and regions may be exaggerated for clarity. Like numbers referto like elements throughout.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. As used herein, the term “and/or” includesany and all combinations of one or more of the associated listed itemsand may be abbreviated as “/”.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first signal could be termed asecond signal, and, similarly, a second signal could be termed a firstsignal without departing from the teachings of the disclosure.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the inventiveconcept. As used herein, the singular forms “a”, “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the present inventive concept willbecome more apparent by describing in detail exemplary embodimentsthereof with reference to the attached drawings in which:

FIG. 1 is a block diagram of a non-volatile memory system according tosome embodiments of the present inventive concept;

FIG. 2 is a circuit diagram of a NAND string of memory transistors inthe memory cell array 231 of a non-volatile memory device according tosome embodiments of the present inventive concept;

FIG. 3 is a threshold voltage distribution diagram showing an example ofthreshold voltage distributions of four logic states of the memory cellsin the memory array 231 of the memory system of FIG. 1;

FIG. 4 is a cross sectional view of two adjacent memory transistors inthe NAND string of FIG. 2;

FIG. 5 is a graph of threshold voltage ratios for explaining the effectof a memory system according to some embodiments of the presentinventive concept;

FIG. 6 is a voltage diagram showing the different levels of passvoltages provided to unselected word lines adjacent to the currentlyselected word line in some embodiments of the present inventive concept;

FIG. 7 is a threshold voltage distribution diagram showing anotherexample of threshold voltage distributions of the four logic states ofmemory cells in the memory array 231 of the memory system of FIG. 1;

FIG. 8 is a voltage diagram showing different pass voltages provided tounselected word lines adjacent to the selected word line so that thethreshold voltage distribution states are as shown in FIG. 7, in otherembodiments of the present inventive concept;

FIG. 9A is a flowchart of a method of providing an operating voltage ina semiconductor memory device according to some embodiments of thepresent inventive concept;

FIG. 9B is a flowchart detailing substeps of applying a first passvoltage in the method of FIG. 9A;

FIG. 10 is a block diagram of a memory card including the non-volatilememory device 120 shown in FIG. 1 according to an exemplaryimplementation of the memory system of FIG. 1;

FIG. 11 is a block diagram of a computer system including thenon-volatile memory of FIG. 1 or FIG. 10 according to another exemplaryimplementation;

FIG. 12 is a block diagram of a memory system 400 implementing a solidstate drive (SSD) and including the non-volatile memory device 120 shownin FIG. 1 according to still another exemplary implementation; and

FIG. 13 is a block diagram of a RAID array including a plurality of thememory system 400 of FIG. 12.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

FIG. 1 is a block diagram of a non-volatile memory system 100 accordingto some embodiments of the present inventive concept. The non-volatilememory system 100 includes a non-volatile memory device 120 and a memorycontroller 110 for controlling the non-volatile memory device 120.

The non-volatile memory device 120 includes a memory cell array 230, anaddress decoder 240, a data write driver/sense amplifier (SA) circuit250, a chip controller 260, a voltage generator 270, and input/output(I/O) circuit 280.

The memory controller 110 includes a static random access memory (SRAM)111, a central processing unit (CPU) 112, a host interface (I/F) 113, acontrol module 114, and a memory I/F 115.

The host I/F 113 includes an interface protocol to communicate with ahost. The SRAM 111 stores data and/or a program in a volatile state. Thememory I/F 115 interfaces with the non-volatile memory device 120. TheCPU 112 performs overall control of writing data to and/or reading datafrom the non-volatile memory device 120.

The control module 114 controls the chip controller 260 to control thelevel of a first pass voltage applied to at least one word line adjacentto a selected word line based on the level of the read voltage appliedto the selected word line. The chip controller 260 may directly orindirectly control the voltage generator 270 to change the level of thefirst pass voltage to a predetermined voltage level to be applied havingthe predetermined level to the at least one word line adjacent to theselected word line.

The memory cell array 230 includes a main area 231 and a spare area 232.The main area 231 may be used to store user data and is thus referred toas a user data area. The spare area may be used to store errorcorrecting code (ECC) data and the level of the read voltage.

The address decoder 240 selects one word line from among a plurality ofword lines in response to a row address, and provides the read voltageto the selected word line, and provides the first pass voltage to atleast one word line adjacent to the selected word line among unselectedword lines, and provides a second pass voltage to the remainingunselected word lines. At this time, the first pass voltage may be equalto or higher than the second pass voltage. The read voltage may be averify read voltage used in incremental step pulse programming (ISPP) ora read voltage used in a random access data read operation.

The write driver/SA circuit 250 is connected to a plurality of bit linesto program data into selected memory cells or to read data from theselected memory cells by sensing and amplifying the data. The writedriver/SA circuit 250 may include a plurality of data storage cells (notshown) that input-buffer a data set to be programmed during a programoperation and output-buffer a data set that has been read from memorycells during a read operation. Each of the data storage cells mayinclude a plurality of latches. The data storage cells may alsooutput-buffer a data set that has been read during a program verifyoperation.

A switching block (not shown) may also be provided between the writedriver/SA circuit 250 and the memory cell array 230 to alternatelyconnect the write driver and the SA to the bit lines.

The chip controller 260 outputs internal control signals (not shown) forcontrolling the operations (e.g., the program operation, the eraseoperation, and the read operation) of the non-volatile memory device 120in response to external commands. The voltage generator 270 generatesoperation voltages (e.g., a program voltage, a pass voltage, and a readvoltage) necessary for the operations of the non-volatile memory device120. The voltages generated by the voltage generator 270 may comprise aprogram operation voltage, a read operation voltage and a verifyoperation voltage.

The chip controller 260 controls the voltage generator 270 to change thelevel of the first pass voltage to the predetermined level and thenprovides the first pass voltage to at least one word line adjacent tothe currently selected word line according to the control of the memorycontroller 110, but the present inventive concept is not restrictedthereto. For instance, the chip controller 260 may control the voltagegenerator 270 to change the level of the first pass voltage to thepredetermined level and then provide the first pass voltage to at leastone word line adjacent to the selected word line, according to thecontrol of the chip controller 260 and without the control of the memorycontroller 110.

The I/O circuit 280 interfaces with an external device, (e.g., thememory controller 110). The I/O circuit 280 may receive commands and thedata to be programmed from the external device and may transmit a statesignal and the data that has been read to the external device.

The memory controller 110 controls overall data exchange between thehost and the non-volatile memory device 120. For instance, the memorycontroller 110 controls the non-volatile memory device 120 according tothe control of the host to write data or read data.

FIG. 2 is a circuit diagram of a NAND string of memory transistors inthe memory cell array 231 of the non-volatile memory device 120according to some embodiments of the present inventive concept. FIG. 2shows a single NAND string in the memory cell array 231.

Referring to FIG. 2, a read voltage V_(READ) output from the voltagegenerator 270 is provided to the currently selected word line WL_(N)among the plurality of word lines WL₀ through WL_(m). A first passvoltage V_(pass)′ is provided to at least one word line among word linesWL_(N−1) and WL_(N+), adjacent to the selected word line WL_(N). Asecond pass voltage V_(pass) is provided to the remaining unselectedword lines.

The level of the first pass voltage V_(pass)′ may be higher than thelevel of the second pass voltage V_(pass), as will be described indetail with reference to FIG. 5 below.

A power supply voltage Vcc is applied to a string selection line SSLconnected to the gate of a first selection transistor ST1. A groundvoltage GND is applied to a ground selection line GSL connected to thegate of a second selection transistor ST2. A predetermined bias voltageV_(bias) is applied to a common source line CSL.

FIG. 3 is a threshold voltage distribution diagram showing an example ofthreshold voltage distribution states of the memory cells in the memoryarray 231 of the memory system of FIG. 1. FIG. 4 is a cross section oftwo adjacent memory transistors in the NAND string of FIG. 2 forexplaining F-poly coupling occurring between memory cells.

Referring to FIG. 3, a multi-level cell (MLC), has four logic states,and each state has a threshold voltage distribution. FIG. 3, shows thethreshold voltage distributions corresponding to a first logic stateState1, a second logic state State2, a third logic state State3, and afourth logic state State4. The threshold voltage distributioncorresponding to each of the first through fourth logic states State1through State4 is wider than desired, leaving a narrower margin betweenadjacent states, due to various causes. For instance, the thresholdvoltage distribution may be wider due to coupling, e.g., F-polycoupling, between adjacent memory cells during programming.

Referring to FIG. 4, the first memory cell MCA is a memory cell that hasbeen programmed to be in one of the first through fourth logic statesState1 through State4 and the second memory cell MCB is a memory cellthat will be programmed to be in one of the first through fourth logicstates State1 through State4.

When the second memory cell MCB is programmed, charges are accumulatedat a floating gate FG2 of the second memory cell MCB. At this time, thevoltage potential of a floating gate FG1 of the first memory cell MCAadjacent to the second memory cell MCB may be increased due to couplingwith the floating gate FG2 of the second memory cell MCB. Such anincreased threshold voltage is still maintained by the coupling betweenthe floating gates FG1 and FG2 even after the programming. Here, thesecond memory cell MCB may be any one of memory cells adjacent to thefirst memory cell MCA in a word line direction or in a bit linedirection. The threshold voltage of the first memory cell MCA that hasbeen programmed may be increased due to the coupling, and therefore, thethreshold voltage distribution may be wider, and the threshold voltagevalue may be increased by more than one adjacent memory cells due to therandomness of the data programmed into adjacent memory cells.Consequently, a fail may occur in reading the first memory cell MCA.

FIG. 5 is a graph for explaining the effect in a memory system accordingto some embodiments of the present inventive concept. Referring to FIGS.2 and 5, the first pass voltage V_(pass)′ higher than the second passvoltage V_(pass) is provided to a word line (e.g., WL_(N−1)) adjacent tothe selected word line WL_(N). For instance, when the second passvoltage V_(pass) is 7 V, the first pass voltage V_(pass)′ may be 8 V(i.e., higher than 7 V).

FIG. 5 shows a ratio

$\frac{V_{{th}\; 2}}{V_{{th}\; 1}}$

of the threshold voltage V_(th2) of a memory cell positioned at theselected word line WL_(N) to a threshold voltage V_(th1) of a memorycell positioned at the unselected word line WL_(N−1) adjacent to theselected word line WL_(N) as a function of the threshold voltage V_(th1)of the memory cell positioned at the unselected word line WL_(N−1)adjacent to the selected word line WL_(N). In other words, the x-axisindicates the threshold voltage V_(th1) and the y-axis indicates

$\frac{V_{{th}\; 2}}{V_{{th}\; 1}}$

in FIG. 5. The ratio

$\frac{V_{{th}\; 2}}{V_{{th}\; 1}}$

is lower for all values of the threshold voltage V_(th1) when the firstpass voltage V_(pass)′ is 8 V (curve 52) than when the first passvoltage V_(pass)′ is 7 V (curve 51).

Accordingly, it can be inferred that the threshold voltage of a memorycell positioned at the selected word line WL_(N) is less affected bycoupling when the first pass voltage V_(pass)′ is 8 V than when thefirst pass voltage V_(pass)′ is 7 V.

FIG. 6 is a voltage diagram showing the different levels of passvoltages provided to unselected word lines adjacent to the currentlyselected word line in some embodiments of the present inventive concept.

Referring to FIGS. 3 and 6, the first pass voltage V_(pass)′ is appliedto the unselected word lines adjacent to the selected word line atdifferent levels. For instance, when a first read voltage V_(RD1) isapplied to the selected word line, the first pass voltage V_(pass)′ maybe 8.5 V. When a second read voltage V_(RD2) is applied to the selectedword line, the first pass voltage V_(pass)′ may be 8 V. When a thirdread voltage V_(RD3) is applied to the selected word line, the firstpass voltage V_(pass)′ may be 7.5 V.

At this time, the level difference V_(S) between the different values ofthe first pass voltage V_(pass)′ may have a predetermined constantdifference value and is 0.5 V in FIG. 6.

As described above, when the first pass voltage V_(pass)′ is applied atdifferent levels according to the level of a read voltage, a readdisturb problem can be mitigated.

FIG. 7 is a threshold voltage distribution diagram showing differentthreshold voltage distributions of the four logic states of the MLCmemory cells in the memory array 231 of the memory system of FIG. 1.FIG. 8 is a voltage diagram showing different pass voltages provided tounselected word lines adjacent to the currently selected word line whenthe threshold voltage distribution of logic states are as shown in FIG.7, in other embodiments of the present inventive concept.

Referring to FIGS. 7 and 8, the first state State1 having the thresholdvoltage distribution shown in FIG. 7 has a negative threshold voltageunlike the example shown in FIG. 3.

At this time, the threshold voltage distribution of logic states may bedivided into the first state State1 having the negative thresholdvoltage and the other states, i.e., the second through fourth stateState2 through State4 having positive threshold voltages. In this case,when a fourth read voltage V_(RD4) is applied to read the first stateState1, the first pass voltage V_(pass)′ may be 8.5 V; otherwise, thefirst pass voltage V_(pass)′ may be 7.5 V.

At this time, the level difference V_(S)′ in the first pass voltageV_(pass)′ may have a predetermined constant difference value and is 1 Vin FIG. 8.

FIG. 9A is a flowchart of a method of providing an operating voltage ina semiconductor memory device according to some embodiments of thepresent inventive concept.

Referring to FIG. 9A, a read voltage is applied to a selected word linein step S100. At this time, the read voltage may be a verify readvoltage used in ISPP or a read voltage used in a random data access readoperation.

A first pass voltage is applied to at least one of word lines adjacentto the selected word line in step S200. A second pass voltage is appliedto the remaining word lines other than the selected word line and the atleast one word line to which the first pass voltage is applied in stepS300. The first pass voltage may be equal to or higher than the secondpass voltage. The steps S100, S200, and S300 may be commencedsequentially (one step commenced after the prior has been commenced) oralternately may be commenced in parallel (commenced at substantially thesame time). In practice the first pass voltage is applied to at leastone of the unselected word lines adjacent to the selected word line (instep S200) while the second pass voltage is applied to the remainingunselected word lines (in step S300) while the read voltage is appliedto the selected word line (in step S100).

FIG. 9B is a flowchart detailing substeps of step S200 in the method ofFIG. 9A. Referring to FIG. 1 and FIGS. 9A and 9B, in step S210, thenon-volatile memory device 120 detects or identifies the read voltageapplied to the selected word line according to the control of the memorycontroller 110 or the chip controller 260. In step S220, thenon-volatile memory device 120 changes and applies the first passvoltage based on the level of the read voltage obtained as a result ofthe detection or identification. For instance, the non-volatile memorydevice 120 may decrease the first pass voltage when the level of theread voltage increases or vice versa. The level difference (incrementVs′) in the first pass voltage may have a predetermined constant value.

FIG. 10 is a block diagram of a memory card including the non-volatilememory device 120 shown in FIG. 1 according to an exemplaryimplementation of the memory system of FIG. 1. The memory card 700 shownin FIG. 10 is implemented as a flash memory card. The memory card 700may includes non-volatile memory device 120 that can control theoperating voltages applied to the selected and adjacent unselected wordlines as explained above, a memory controller 710, and a card interface720 to interface with a host.

The memory controller 710 controls data transmission between thenon-volatile memory device 120 and the card interface 720.

In some an exemplary implementations, the memory card 700 of FIG. 10 maybe implemented as a smart card.

According to an exemplary implementation, the card interface 720 may bea secure digital (SD) card interface or a multi-media card (MMC)interface. However, implementation are not limited thereto. The cardinterface 720 may interface for data exchange between the host and thememory controller 710 according to a communication protocol.

When the memory card 700 is connected to a host, e.g., a PC, a tabletPC, a digital camera, a digital audio player, a cellular phone, aconsole video game hardware, a digital set-top box, and so forth, thememory controller 710 of the memory card 700 may transmit or receivedata stored in the non-volatile memory device 120 with the host.

FIG. 11 illustrates a block diagram of a memory system 300 including thenon-volatile memory device 120 shown in FIG. 1 or the memory card 700 ofFIG. 10 according to various other exemplary embodiments.

Referring to FIG. 11, the memory system 300 may be implemented in theform of a cellular phone, a smart phone, a PDA (personal digitalassistant), a digital camera, a portable game console, a MP3 player, aHDTV (High-definition television), a GPS (Global Positioning System), anavigator, a CE (consumer equipment), a digital settop box) or an IT(information technology) device.

The memory system 300 may include a CPU 310 and a non-volatile memorydevice 120 which are connected with each other through a system bus 301.According to another exemplary embodiment, the memory system 300 mayinclude the CPU 310 and the memory card 700 of FIG. 10, which areconnected with each other through the system bus 301.

The CPU 310 may control operations of the non-volatile memory device120, e.g., a program operation, a read operation, an erase operation oran operation of transmitting data to the host. Alternatively, the memorycontroller 710 of the memory card 700 may control operations of thenon-volatile memory device 120, e.g., a program operation, a readoperation, an erase operation or an operation of transmitting data tothe host.

The memory device 320 connected to the bus 301 may be used as the randomaccess system memory (RAM) of the CPU 310. The memory device 320 may bea DRAM, or a SRAM. The memory device 320 may be a memory module e.g., aSIMM (single in-line memory module) or a DIMM (dual in-line memorymodule). In alternative embodiments, the memory device 320 may be amemory module that includes a plurality of the non-volatile memorydevice 120 illustrated in FIG. 1.

The memory system 300 may include a first user interface 330 such as adisplay or a touch pad. And, the memory system 300 may further include asecond user interface 340 such as an input/output interface. The seconduser interface 340 may be an output device such as a printer or an inputdevice such as a keyboard or a mouse. According to an exemplaryembodiment, the first user interface 330 may be replaced with a CMOSimage sensor. The CMOS image sensor may convert an optical image to adigital image, and the digital image will be stored in the memory device120 (or the memory card 700) under control of the CPU 310.

FIG. 12 is a block diagram of a memory system 400 implementing a solidstate drive (SSD) and including the non-volatile memory device 120 shownin FIG. 1 according to still another exemplary implementation. Referringto FIG. 12, the memory system 400 implements a solid state drive (SSD).

The memory system 400 may include a plurality of non-volatile memorydevices 120 and a memory controller 410 controlling the data accessfunctions of each of the plurality of non-volatile memory devices 120.Each of the plurality of non-volatile memory devices 120, under thecontrol of the memory controller 410, can adaptively control accessfunctions to determine or verify whether a selected non-volatile memorycell among a plurality of non-volatile memory cells included in each ofthe plurality of non-volatile memory devices 120 is programmed orerased.

FIG. 13 is a block diagram of a RAID array including a plurality of thememory system 400 of FIG. 12. Referring to FIGS. 12 and 13, a RAID array500 may be a redundant array of independent disks (RAID) system thatincludes a RAID controller 510 and a plurality of memory systems 400-1to 400-S of FIG. 12, where S is a natural number.

Each of the plurality of memory systems 400-1 to 400-S may alternativelybe a memory card 700 of FIG. 10. The plurality of memory systems 400-1to 400-S may compose a RAID array having a user selected redundancylevel (RAID level). Each of the plurality of memory systems 400-1 to400-S includes one of the memory controller 410 of FIG. 12 to controlthe function of the plurality of the non-volatile memory devices 120therein. The RAID controller 510 controls the function of the pluralityof memory systems 400-1 to 400-S. The RAID array 500 may be included ina personal computer (PC) or in one SSD unit for use therein.

During a write (or program) operation, the RAID controller 510 outputs awrite (or program) data output command from the host to one or more ofthe plurality of memory systems 400-1 to 400-S according to a selectedone of a plurality of RAID levels in response to a write (or program)command output from the host.

Additionally, during a read operation, the RAID controller 510 maytransmit data read from one or more of the plurality of memory systems400-1 to 400-S to the host according to the selected one of a pluralityof RAID levels in response to a read command output from the host.

The present inventive concept may be implemented with hardware such asmodules, or software such as algorithm or firmware. The algorithm orfirmware may be implemented as computer readable codes and/or programson a computer readable recording medium. The method of providing anoperating voltage in a semiconductor memory device according to someembodiments may be implemented by executing the computer program forexecuting the method of providing an operating voltage in asemiconductor memory device stored in the computer readable recordingmedium.

The computer readable recording medium is any data storage device thatcan store data which can be thereafter read by a computer system. Moreparticularly, the computer readable recording medium may be, e.g., atangible, non-transitory recording medium. Examples of the computerreadable recording medium include read-only memory (ROM), random-accessmemory (RAM), CD-ROMs, magnetic tapes, floppy disks, and optical datastorage devices. The program codes for executing a method of upgradingan operation program in an RFID system may be transmitted in the form ofcarrier waves (such as data transmission through the Internet).

The computer readable recording medium can also be distributed overnetwork coupled computer systems so that the computer readable code isstored and/or executed in a distributed fashion. Also, functionalprograms, codes, and/or code segments for realizing embodiments can beeasily construed by programmers skilled in the art to which theembodiments pertain.

As described above, according to some embodiments of the presentinventive concept, the characteristic of the threshold voltagedistribution of the logic states of multilevel memory cells (MLCs) isimproved.

Exemplary embodiments have been disclosed herein, and although specificterms are employed, they are used and are to be interpreted in a genericand descriptive sense only and not for purpose of limitation. In someinstances it would be apparent to one of ordinary skill in the artviewing of the present application, that features, characteristics,and/or elements described in connection with a particular embodiment maybe used singly or in combination with features, characteristics, and/orelements described in connection with other embodiments unless otherwisespecifically indicated. Accordingly, it will be understood by those ofskill in the art viewing of the present application that various changesin form and details may be made without departing from the spirit andscope of the present inventive concept as set forth in the followingclaims.

What is claimed is:
 1. A method of providing an operating voltage in amemory device, the method comprising: applying a first read voltage to aselected word line of a NAND string; applying a first pass voltage to atleast one unselected word line among unselected word lines adjacent tothe selected word line of the NAND string; applying a second passvoltage to at least one other unselected word lines of the NAND string;applying a second read voltage to the selected word line of the NANDstring; applying a third pass voltage to at least one unselected wordline to which the first pass voltage is applied; and applying a fourthpass voltage to at least one other unselected word lines to which thesecond pass voltage is applied; wherein a level of the first passvoltage is higher than a level of the second pass voltage, wherein thelevel of the first pass voltage is different from the level of the thirdpass voltage.
 2. The method of claim 1, wherein if a level of the firstread voltage is higher than a level of the second read voltage, thelevel of the first pass voltage is higher than the level of the thirdpass voltage, wherein if the level of the first read voltage is lowerthan the level of the second read voltage, the level of the first passvoltage is lower than the level of the third pass voltage.
 3. The methodof claim 1, wherein applying the first pass voltage comprises detectingthe level of the first read voltage and selecting the level of the firstpass voltage according to the level of the first read voltage, whereinapplying the third pass voltage comprises detecting the level of thesecond read voltage and selecting the level of the third pass voltageaccording to the level of the second read voltage.
 4. The method ofclaim 1, wherein applying the second pass voltage includes: applying thesecond pass voltage to at least one other unselected word line amongunselected word lines disposed on the bit line side of the selected wordline in the NAND string; and applying the second pass voltage to atleast one of the other unselected word lines among unselected word linesdisposed on the common source side of the selected word line in the NANDstring, wherein applying the fourth pass voltage includes: applying thefourth pass voltage to at least one other unselected word line amongunselected word lines disposed on the bit line side of the selected wordline in the NAND string; and applying the fourth pass voltage to atleast one of the other unselected word lines among unselected word linesdisposed on the common source side of the selected word line in the NANDstring.
 5. The method of claim 1, wherein the selecting and applying theselected higher level of the first pass voltage comprises setting thevoltage difference between the first pass voltage and the first readvoltage to a predetermined value, wherein the selecting and applying theselected higher level of the third pass voltage comprises setting thevoltage difference between the third pass voltage and the second readvoltage to a predetermined value.
 6. The method of claim 1, wherein oneof the first read voltage and the second read voltage is a read voltageused in incremental step pulse programming (ISPP) or a read voltage usedin a random access read operation.
 7. The method of claim 1, wherein theselecting and applying the first pass voltage comprises applying thefirst pass voltage at different levels according to whether the firstread voltage is a negative voltage or not a negative voltage, whereinthe selecting and applying the third pass voltage comprises applying thethird pass voltage at different levels according to whether the secondread voltage is a negative voltage or not a negative voltage.
 8. Anon-transient computer readable storage medium containing program codesconfigured for execution by a processor to carry out the method ofclaim
 1. 9. A memory device comprising: a memory cell array including astring of memory transistors connected to a plurality of word lines; avoltage generator configured to provide an operating voltage for anoperation in the memory cell array; and a chip controller configured tocontrol the voltage generator to apply a first read voltage to aselected word line, apply a first pass voltage to at least oneunselected word line among unselected word lines adjacent to theselected word line, apply a second pass voltage to the other unselectedword lines, apply a second read voltage to the selected word line, applya third pass voltage to at least one unselected word line to which thefirst pass voltage is applied, and apply a fourth pass voltage to theother unselected word lines to which the second pass voltage is applied,wherein a level of the first pass voltage is higher than a level of thesecond pass voltage, wherein the level of the first pass voltage isdifferent from the level of the third pass voltage.
 10. The method ofclaim 9, wherein if a level of the first read voltage is higher than alevel of the second read voltage, the level of the first pass voltage ishigher than the level of the third pass voltage, wherein if the level ofthe first read voltage is lower than the level of the second readvoltage, the level of the first pass voltage is lower than the level ofthe third pass voltage.
 11. The memory device of claim 9, wherein thechip controller controls the voltage generator to set the level of thefirst pass voltage and the level of the third pass voltage respectivelybased on the level of the first read voltage and the level of the secondread voltage.
 12. The memory device of claim 9, wherein applying thesecond pass voltage includes: applying the second pass voltage to atleast one other unselected word line among unselected word linesdisposed on the bit line side of the selected word line in the NANDstring; and applying the second pass voltage to at least one of theother unselected word lines among unselected word lines disposed on thecommon source side of the selected word line in the NAND string, whereinapplying the fourth pass voltage includes: applying the fourth passvoltage to at least one other unselected word line among unselected wordlines disposed on the bit line side of the selected word line in theNAND string; and applying the fourth pass voltage to at least one of theother unselected word lines among unselected word lines disposed on thecommon source side of the selected word line in the NAND string.
 13. Thememory device of claim 9, wherein the chip controller controls thevoltage generator to set the level difference between the first passvoltage and the first read voltage to a predetermined value, wherein thechip controller controls the voltage generator to set the leveldifference between the third pass voltage and the second read voltage toa predetermined value.
 14. The memory device of claim 9, wherein one ofthe first read voltage and the second read voltage is a read voltageused in incremental step pulse programming (ISPP) or a read voltage usedin a random access read operation.
 15. The memory device of claim 9,wherein the chip controller applies the first pass voltage at differentlevels according to whether the first read voltage is a negative voltageor not a negative voltage, wherein the chip controller applies the thirdpass voltage at different levels according to whether the second readvoltage is a negative voltage or not a negative voltage.
 16. A memorysystem comprising: a memory device including an array of memorytransistors connected to a plurality of word lines; and a memorycontroller configured to control the memory device to apply a first readvoltage to a selected word line, apply a first pass voltage to at leastone unselected word line among unselected word lines adjacent to theselected word line, apply a second pass voltage to the other unselectedword lines, apply a second read voltage to the selected word line, applya third pass voltage to at least one unselected word line to which thefirst pass voltage is applied, and apply a fourth pass voltage to theother unselected word lines to which the second pass voltage is applied,wherein a level of the first pass voltage is higher than a level of thesecond pass voltage, wherein the level of the first pass voltage isdifferent from the level of the third pass voltage.